View CXK77K36R320GB_4104109.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SONY
Description
CXK77K36R320GB
3/33/4
Preliminary
32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K differential input clock. During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered. During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered. Sleep (power down) capability is provided via the ZZ input signal. Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external control resistor RQ between ZQ and VSS, the impedance of the output drivers can be precisely controlled. 333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
* 3 Speed Bins -3 -33 -4 Cycle Time / Access Time 3.0ns / 1.6ns 3.3ns / 1.6ns 4.0ns / 2.0ns
* Single 2.5V power supply (VDD): 2.5V 5% Note: 1.8V VDD is also supported. Please contact Sony Memory Marketing Department for further information. * Dedicated output supply voltage (VDDQ): 1.5V 0.1V Note: 1.8V VDDQ is also supported. Please contact Sony Memory Marketing Department for further information. * HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical * Register - Register (R-R) read protocol * Late Write (LW) write protocol * Full read/write coherency * Byte Write capability * Differential input clocks (K/K) * Asynchronous output enable (G) * Sleep (power down) mode via dedicated mode pin (ZZ) * Programmable output driver impedance * JTAG boundary scan (subset of IEEE standard 1149.1) * 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
32Mb LW R-R, rev 0.6
1 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB 1Mb x 36 Pin Assignment (Top View)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 SA SA SA DQc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQd SA NC (x18) TMS 3 SA SA SA V SS V SS V SS SBWc V SS VREF V SS SBWd V SS V SS V SS M1 (1) SA TDI 4 NC SA (32M) VDD ZQ SS G NC NC VDD K K SW SA SA VDD SA (x36) TCK 5 SA SA SA V SS V SS V SS SBWb V SS VREF V SS SBWa V SS V SS V SS M2 (2) SA TDO 6 SA SA SA DQb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQa SA NC (x18) RSVD (3)
Preliminary
7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Notes: 1. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied "low" in this device. 2. Pad Location 5R is defined as an M2 mode pin in LW SRAMs. However, it must be tied "high" in this device. 3. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
32Mb LW R-R, rev 0.6
2 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB Pin Description
Preliminary
Symbol SA DQa, DQb DQc, DQd
Type Input I/O
Description Synchronous Address Inputs - Registered on the rising edge of K. Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations. Driven from the rising edge of K during read operations. DQa - indicates Data Byte a DQb - indicates Data Byte b DQc - indicates Data Byte c DQd - indicates Data Byte d Differential Input Clocks Synchronous Select Input - Registered on the rising edge of K. SS = 0 enables the device to accept read and write commands SS = 1 disables the device Synchronous Write Enable Input - Registered on the rising edge of K. SW = 0 specifies a write operation when the device is enabled SW = 1 specifies a read operation when the device is enabled Synchronous Byte Write Enable Inputs - Registered on the rising edge of K. SBWa = 0 specifies write Data Byte a during a write operation SBWb = 0 specifies write Data Byte b during a write operation SBWc = 0 specifies write Data Byte c during a write operation SBWd = 0 specifies write Data Byte d during a write operation Asynchronous Output Enable Input - Deasserted (high) disables the data output drivers. Asynchronous Sleep Mode Input - Asserted (high) forces the device into low-power mode. Read Operation Protocol Select - These mode pins must be tied "low" and "high" respectively to select Register - Register read operations. Output Driver Impedance Control Resistor Input - This pin must be connected to VSS through an external resistor RQ to program data output driver impedance. See the Programmable Output Driver Impedance section for further information. 2.5V Core Power Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Input Reference Voltage - Input buffer threshold voltage. Ground
K, K SS
Input Input
SW
Input
SBWa, SBWb SBWc, SBWd
Input
G ZZ M1, M2 ZQ
Input Input Input Input
VDD VDDQ VREF VSS TCK TMS TDI TDO RSVD NC Input Input Input Output
JTAG Clock JTAG Mode Select - Weakly pulled "high" internally. JTAG Data In - Weakly pulled "high" internally. JTAG Data Out Reserved - This pin is reserved for Sony test purposes. It must be left unconnected. No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS.
32Mb LW R-R, rev 0.6
3 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
*Clock Truth Table
K X Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care". 2. "***" indicates that the input requirement or output state is determined by the previous operation. 3. DQs are tri-stated in response to Write and Deselect commands, one cycle after the command is sampled. ZZ 1 0 0 0 0 0 0 SS (tn) X 1 0 0 0 0 0 SW (tn) X X 1 1 0 0 0 SBWx (tn) X X X X 0 X 1 G X X 1 0 X X X Operation Sleep (Power Down) Mode Deselect Read Read Write All Bytes Write Bytes With SBWx = 0 Abort Write DQ (tn) Hi - Z *** Hi - Z *** *** *** *** DQ (tn+1) Hi - Z Hi - Z Hi - Z Q(tn) D(tn) D(tn) Hi - Z
*Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output drivers are disabled and the SRAM begins to draw standby current. Contents of the memory array are preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time (tZZR) must be met before the SRAM can resume normal operation.
*Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor RQ connected between the SRAM's ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See the DC Electrical Characteristics section for further information. Output Driver Impedance Power-Up Requirements Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recommended that Read operations not be initiated until after the initial 8192 cycles have elapsed. Output Driver Impedance Updates Output driver impedance is updated during Write and Deselect operations when the output driver is disabled.
*Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: V SS, VDD, VDDQ, VREF, and Inputs. VDDQ should never exceed V DD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
32Mb LW R-R, rev 0.6
4 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
*Absolute Maximum Ratings
Parameter Supply Voltage Output Supply Voltage Input Voltage (Address, Control, Data, Clock) Input Voltage (M1, M2) Input Voltage (TCK, TMS, TDI) Operating Temperature Junction Temperature Storage Temperature Symbol VDD VDDQ VIN VMIN VTIN TA TJ TSTG Rating -0.5 to +3.2 -0.5 to +2.3 -0.5 to VDDQ + 0.5 (2.3V max) -0.5 to VDD + 0.5 (3.2V max) -0.5 to +3.8V 0 to 85 0 to 110 -55 to 150 Units V V V V V C C C
Notes: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
*BGA Package Thermal Characteristics
Parameter Junction to Case Temperature Symbol JC Rating 3.6 Units C/W
*I/O Capacitance
Parameter Address Input Capacitance Control Clock Output Capacitance Data Symbol CIN CIN CKIN COUT Test conditions VIN = 0V VIN = 0V VKIN = 0V VOUT = 0V Min ---------
(TA = 25oC, f = 1 MHz) Max 4.0 4.0 4.5 5.0 Units pF pF pF pF
Note: These parameters are sampled and are not 100% tested.
32Mb LW R-R, rev 0.6
5 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
(VSS = 0V, TA = 0 to 85oC)
*DC Recommended Operating Conditions
Parameter Supply Voltage Output Supply Voltage Input Reference Voltage Input High Voltage (Address, Control, Data) Input Low Voltage (Address, Control, Data) Input High Voltage (M1, M2) Input Low Voltage (M1, M2) Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Symbol VDD VDDQ VREF VIH VIL VMIH VMIL VKIN VDIF VCM Min 2.37 1.4 VDDQ/2 - 0.1 VREF + 0.1 -0.3 VREF + 0.3 -0.3 -0.3 0.2 VDDQ/2 - 0.1 Typ 2.5 1.5 VDDQ/2 ------------VDDQ/2
Max 2.63 1.6 VDDQ/2 + 0.1 VDDQ + 0.3 VREF - 0.1 VDD + 0.3 VREF - 0.3 VDDQ + 0.3 VDDQ + 0.6 VDDQ/2 + 0.1
Units V V V V V V V V V V
Notes 1 2 3 4 5
1. V DD = 1.8V 0.1V is also supported. Please contact Sony Memory Marketing Department for further information. 2. V DDQ = 1.8V 0.1V is also supported. Please contact Sony Memory Marketing Department for further information. 3. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component. 4. V IH (max) AC = VDDQ + 0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4). 5. V IL (min) AC = -0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4).
32Mb LW R-R, rev 0.6
6 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
(V DD = 2.5V 5%, V SS = 0V, TA = 0 to 85oC)
*DC Electrical Characteristics
Parameter Input Leakage Current (Address, Control, Clock) Input Leakage Current (M1, M2) Output Leakage Current Symbol ILI IMLI ILO IDD-3 IDD-33 IDD-4 ISB Test Conditions VIN = V SS to VDDQ VMIN = VSS to V DD VOUT = VSS to VDDQ G = VIH IOUT = 0 mA SS = V IL, ZZ = VIL IOUT = 0 mA ZZ = VIH IOH = -6.0 mA RQ = 250 IOL = 6.0 mA RQ = 250 VOH, VOL = V DDQ/2 RQ < 150 Output Driver Impedance ROUT VOH, VOL = VDDQ/2 150 RQ 300 VOH, VOL = VDDQ/2 RQ > 300 1. This parameter is guaranteed at TA = 0 to 55oC.
Min -5 -5
Typ -----
Max 5 5
Units uA uA
Notes
-5 ---------
-----------
5 650 600 540 180
uA
Average Power Supply Operating Current Power Supply Standby Current Output High Voltage
mA
mA
1
VOH
VDDQ - 0.4
---
---
V
Output Low Voltage
VOL
---
---
0.4 35 (30*1.15) (RQ/5)* 1.15 ---
V
--(RQ/5)* 0.85 51 (60*0.85)
---
2
RQ/5
---
3
2. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS. 3. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ.
32Mb LW R-R, rev 0.6
7 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary (VDD = 2.5V 5%, VSS = 0V, TA = 0 to 85oC)
*AC Electrical Characteristics
-3 Parameter Input Cycle Time Input Clock High Pulse Width Input Clock Low Pulse Width Address Input Setup Time Address Input Hold Time Write Enable Input Setup Time Write Enable Input Hold Time Sync Select Input Setup Time Sync Select Input Hold Time Data Input Setup Time Data Input Hold Time Input Clock High to Output Data Valid Input Clock High to Output Data Hold Input Clock High to Output Data Low-Z Input Clock High to Output Data High-Z Output Enable Low to Output Data Valid Output Enable Low to Output Data Low-Z Output Enable High to Output Data High-Z Sleep Mode Enable Time Sleep Mode Recovery Time Symbol Min tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ tZZE tZZR 3.0 1.2 1.2 0.3 0.5 0.3 0.5 0.3 0.5 0.3 0.5 --0.65 0.65 0.65 --0.3 ----20 Max ----------------------1.6 ----1.8 2.5 --2.5 15 ---
-33 Min 3.3 1.3 1.3 0.3 0.6 0.3 0.6 0.3 0.6 0.3 0.6 --0.65 0.65 0.65 --0.3 ----20 Max ----------------------1.6 ----1.8 2.5 --2.5 15 --Min 4.0 1.5 1.5 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 --0.65 0.65 0.65 --0.3 ----20
-4 Units Max ----------------------2.0 ----2.2 2.5 --2.5 15 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2 2 2 2,3 2,3 1 1 1 1 Notes
1. These parameters are measured from VREF 200mV to the clock mid-point. 2. These parameters are guaranteed by design through extensive corner-lot characterization. 3. These parameters are measured at 50mV from steady state voltage.
32Mb LW R-R, rev 0.6
8 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
*AC Test Conditions
Item Input Reference Voltage Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions VKIH VKIL VCM Symbol VREF VIH VIL
(VDD = 2.5V 5%, VDDQ = 1.5V 0.1V, TA = 0 to 85C) Conditions 0.75 1.25 0.25 2.0 0.75 1.25 0.25 0.75 2.0 K/K cross 0.75 RQ = 250 Units V V V V/ns V V V V V/ns V V See Figure 1 below VDIF = 1.0V VDIF = 1.0V Notes
Figure 1: AC Test Output Load
16.7 50 16.7 DQ 16.7 50
50 0.75V
50 0.75V
32Mb LW R-R, rev 0.6
9 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB Read-Write-Read Timing Diagram Synchronously Controlled via SS and Deselect Operations (G = Low)
Figure 2
Preliminary
Read
Read
Read
Deselect
Deselect
Write
Write
Write
Read
Read
Read
K
K
tKHKH tKHKL tKLKH tAVKH tKHAX
SA
A1
A2
A3
A4
tSVKH tKHSX
A5
A6
A7
A8
A9
SS
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
G = VIL
tKHQV tKHQX tKHQZ tDVKH tKHDX tKHQX1
DQ
Q1
Q2
Q3
D4
D5
D6
Q7
Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus
transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient.
32Mb LW R-R, rev 0.6
10 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
Read-Write-Read Timing Diagram Asynchronously Controlled via G and Dummy Read Operations (SS = Low)
Figure 3
Read Read Read Dummy Read Dummy Read Write Write Write Read Read Read
K
K
tKHKH tKHKL tKLKH tAVKH tKHAX
SA
A1
A2
A3
A4
A5
A6
A7
A8
A9
SS = VIL
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
G
tGLQV tKHQV tKHQX tGHQZ tKHQZ tDVKH tKHDX tGLQX tKHQX1
DQ
Q1
Q2
Q3
D4
D5
D6
Q7
Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient.
32Mb LW R-R, rev 0.6
11 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB Sleep (Power-Down) Mode Timing Diagram
Figure 4
Preliminary
Read (note 1)
Deselect (note 2)
Deselect (note 3)
Deselect (note 4)
Read (note 5)
Read
Read
K
K
SA
A1
A2
A3
A4
SS
SW
SBWx
G = VIL
tZZE
Begin ISB
tZZR
ZZ
DQ
Q1
Q2
Notes: 1: This can be any operation. The depiction of a Read operation here is provided only as an example. 2: Before ZZ is asserted, at least two (2) Deselect operations must be initiated after the last Read or Write operation is initiated, in order to ensure the successful completion of the last Read or Write operation. 3: While ZZ is asserted, all of the SRAM's address, control, data, and clock inputs are ignored. 4: After ZZ is deasserted, Deselect operations must be initiated until the specified recovery time (tZZR) has been met. Read and Write operations may NOT be initiated during this time. 5: This can be any operation. The depiction of a Read operation here is provided only as an example.
32Mb LW R-R, rev 0.6
12 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
*Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied "low" to prevent clocking the SRAM. TMS and TDI should either be tied "high" through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device. (VDD = 2.5V 5%, VSS = 0V, TA = 0 to 85C) Test Conditions ----ITOH = -100uA ITOL = 100uA ITOH = -8.0mA ITOL = 8.0mA VTIN = VSS to 3.3V Min 1.4 -0.3 VDD - 0.1 --VDD - 0.4 ---10 Max 3.6 0.8 --0.1 --0.4 10 Units V V V V V V uA
JTAG DC Recommended Operating Conditions
Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Voltage (CMOS) JTAG Output Low Voltage (CMOS) JTAG Output High Voltage (TTL) JTAG Output Low Voltage (TTL) JTAG Input Leakage Current Symbol VTIH VTIL VTOH VTOL VTOH VTOL ITLI
JTAG AC Test Conditions
Parameter JTAG Input High Level JTAG Input Low Level JTAG Input Rise & Fall Time JTAG Input Reference Level JTAG Output Reference Level JTAG Output Load Condition Symbol VTIH VTIL
(VDD = 2.5V 5%, VSS = 0V, TA = 0 to 85C) Conditions 2.5 0.0 1.0 1.25 1.25 Units V V V/ns V V See Fig.1 (page 9) Notes
32Mb LW R-R, rev 0.6
13 / 22
March 16, 2004
SONY(R)
JTAG AC Electrical Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time TMS Hold Time TDI Setup Time TDI Hold Time
CXK77K36R320GB
Preliminary
Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX
Min 50 20 20 5 5 5 5 5 5
Max
Unit ns ns ns ns ns ns ns ns ns
Capture Setup Time (Address, Control, Data, Clock) Capture Hold Time (Address, Control, Data, Clock) TCK Low to TDO Valid TCK Low to TDO Hold
10 0
ns ns
JTAG Timing Diagram
Figure 5
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
TMS
tDVTH
tTHDX
TDI
tTLQV tTLQX
TDO
32Mb LW R-R, rev 0.6
14 / 22
March 16, 2004
SONY(R)
TAP Controller
CXK77K36R320GB
Preliminary
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the "Test-Logic Reset" state in one of two ways: 1. At power up. 2. When a logic "1" is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the "Shift-IR" state or the "Shift-DR" state. The TDO output driver is active only when the TAP Controller is in either the "Shift-IR" state or the "Shift-DR" state. TAP Controller State Diagram
Figure 6 1
Test-Logic Reset
0 0
Run-Test / Idle
1
Select-DR
1
Select-IR
1
0 1
Capture-DR
0 1
Capture-IR
0
Shift-DR
0 0
Shift-IR
0
1 1
Exit1-DR
1 1
Exit1-IR
0
Pause-DR
0 0
Pause-IR
0
1
Exit2-DR
1 0
Exit2-IR
0
1
Update-DR
1
Update-IR
1
0
1
0
32Mb LW R-R, rev 0.6
15 / 22
March 16, 2004
SONY(R)
TAP Registers
CXK77K36R320GB
Preliminary
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) from the falling edge of TCK. They are divided into two groups: "Instruction Registers" (IR), which are manipulated via the "IR" states in the TAP Controller, and "Data Registers" (DR), which are manipulated via the "DR" states in the TAP Controller. Instruction Register (IR - 3 Bits) The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the "Test-Logic Reset" and "Capture-IR" states. It is inserted between TDI and TDO when the TAP Controller is in the "Shift-IR" state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed until the TAP Controller has reached the "Update-IR" state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) 000 001 Instruction BYPASS IDCODE See code "111". Loads a predefined device- and manufacturer-specific identification code into the ID Register when the TAP Controller is in the "Capture-DR" state, and inserts the ID Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. See the ID Register description for more information. 010 SAMPLE-Z Loads the individual logic states of all signals composing the SRAM's I/O ring into the Boundary Scan Register when the TAP Controller is in the "Capture-DR" state, and inserts the Boundary Scan Register between TDI and TDO when the TAP Controller is in the "ShiftDR" state. Also disables the SRAM's data output drivers. See the Boundary Scan Register description for more information. 011 100 PRIVATE SAMPLE Do not use. Reserved for manufacturer use only. Loads the individual logic states of all signals composing the SRAM's I/O ring into the Boundary Scan Register when the TAP Controller is in the "Capture-DR" state, and inserts the Boundary Scan Register between TDI and TDO when the TAP Controller is in the "ShiftDR" state. See the Boundary Scan Register description for more information. 101 110 111 PRIVATE PRIVATE BYPASS Do not use. Reserved for manufacturer use only. Do not use. Reserved for manufacturer use only. Loads a logic "0" into the Bypass Register when the TAP Controller is in the "Capture-DR" state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. See the Bypass Register description for more information. Bit 0 is the LSB and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Description
32Mb LW R-R, rev 0.6
16 / 22
March 16, 2004
SONY(R)
Bypass Register (DR - 1 Bit)
CXK77K36R320GB
Preliminary
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic "0" when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the "Shift-DR" state. ID Register (DR - 32 Bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the "Shift-DR" state. The ID Register is 32 bits wide, and contains the following information: Revision Number (31:28) xxxx Part Number (27:12) 0000 0000 0111 0011 Sony ID (11:1) 0000 1110 001 Start Bit (0) 1
Device 1Mb x 36
Bit 0 is the LSB and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Boundary Scan Registers (DR - 70 Bits) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual logic states of all signals composing the SRAM's I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the "ShiftDR" state. The Boundary Scan Register contains the following bits: 1Mb x 36 DQ SA K, K SS, SW, SBWx G, ZZ ZQ, M1, M2 Place Holder 36 20 2 6 2 3 1
Note: K and K are connected to a differential input receiver that generates a single-ended input clock signal to the device. Therefore, in order to capture deterministic values for these signals in the Boundary Scan Register, they must be at opposite logic levels when sampled. Note: When an external resistor RQ is connected between the ZQ pin and VSS, the value of the ZQ signal captured in the Boundary Scan Register is non-deterministic. Note: Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected to V SS internally, regardless of pin connection externally.
32Mb LW R-R, rev 0.6
17 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
Boundary Scan Register Bit Order Assignments The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 70 is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 1Mb x 36 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal M2 SA SA SA SA ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa SBWa K K G SBWb DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA SA SA SA Pad 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal SA SA SA SA SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc SBWc ZQ SS SA NC
(1)
Pad 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4B 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R
SW SBWd DQd DQd DQd DQd DQd DQd DQd DQd DQd SA SA SA M1
Note 1: NC pin at pad location 4H is connected to V SS internally, regardless of pin connection externally.
32Mb LW R-R, rev 0.6
18 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB
Preliminary
*Ordering Information
Part Number CXK77K36R320GB-3 CXK77K36R320GB-33 CXK77K36R320GB-4 VDD 2.5V 2.5V 2.5V I/O Type HSTL HSTL HSTL Size 1Mb x 36 1Mb x 36 1Mb x 36 Speed (Cycle Time / Access Time) 3.0ns / 1.6ns 3.3ns / 1.6ns 4.0ns / 2.0ns
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
32Mb LW R-R, rev 0.6
19 / 22
March 16, 2004
SONY(R)
CXK77K36R320GB 119 Pin BGA Package Dimensions
Preliminary
2.1 0.3 0.84 14.0 13.0 B A 0.6 0.1 X S 3.19 U T R P N M L K J H G F E D C B A 12345 67 0.75 0.15 0.4 0.2 SA S B 7.62 1.27
22.0
21.0
1.27
0.35 S
C 3-
1.0
C
X4 0.20
1. 5
0.6 0.1 1.5
0.15
S
DET AIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE BGA-119P-021 BGA119-P-1422 BORAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 1.1g
This product utilizes lead (Pb) as one of the elements composing the package solder ball. The quantity of lead (Pb) per package is approxmiately 70.81mg (1.7mg per ball * 119 balls * 35%). Lead (Pb) has been shown to be hazardous to the environment, and therefore may be subject to regulations within each country.
32Mb LW R-R, rev 0.6
20 / 22
20.32
March 16, 2004
C 47 1.
SONY(R)
CXK77K36R320GB
Preliminary
*Revision History
Rev. # rev 0.0 rev 0.1 Rev. Date 11/30/01 03/22/02 Initial Version 1. Modified BGA Package Thermal Characteristics section (p. 6). 1.0 C/W to 3.6 C/W JC 2. Modified DC Recommended Operating Conditions section (p. 7). VDDQ (max) VDD to 1.6V VREF, V CM (max) 1.0V to 0.85V Added note 1 regarding 2.5V VDD support. Added note 2 regarding 1.8V VDDQ support. 3. Modified DC Electrical Characteristics section (p. 8). ROUT RQ/5 10% (GBD) to RQ/5 15% (TESTED) 4. Modified AC Electrical Characteristics section (p. 9). Removed "-25" bin. Added "-33" bin. -3 tKHQV 1.7ns to 1.5ns tKHQZ, tGLQV, tGHQZ 1.9ns to 1.7ns 5. Removed 1.8V VDDQ AC Test Conditions. 6. Modified JTAG DC Recommended Operating Conditions section (p. 14). VTIH (min) 1.2V to 1.4V VTIL (max) 0.6V to 0.8V 7. Modified JTAG Instruction Register definition (p. 17). Changed codes "011" and "110" from BYPASS to PRIVATE. 8. Modified 119 Pin BGA Package Dimensions section (p. 21). Changed package from FC-BGA to WB-BGA. 1. Modified DC Recommended Operating Conditions section (p. 7). VDDQ (max) 1.6V to VDD VREF, V CM (min) 0.65V to V DDQ/2 - 0.1V VREF, V CM (max) 0.85V to VDDQ/2 + 0.1V 2. Added 1.8V V DDQ AC Test Conditions (p. 11). 1. Modified AC Electrical Characteristics section (p. 9). -3, -33 tAVKH, tWVKH, tSVKH, tDVKH -3, -33 tKHAX, tKHWX, tKHSX, tKHDX 2. Modified JTAG DC Recommended Operating Conditions section (p. 15). VTIH (min) VTIL (max) 3. Modified JTAG AC Electrical Characteristics section (p.16). TCK Cycle Time TCK High / Low Pulse Widths TMS/TDI Input Setup & Hold Times TDO Output Valid Time Added Capture Setup & Hold Times 0.5ns to 0.3ns 0.5ns to 0.3ns 1.4V to 1.2V 0.8V to 0.6V 100ns to 50ns 40ns to 20ns 10ns to 5ns 20ns to 10ns 5ns Description of Modification
rev 0.2
04/02/02
rev 0.3
06/24/02
rev 0.4
02/05/03
1. Removed all x18 information (created separate x18 data sheet). 2. Changed VDD from 1.8V nominal to 2.5V nominal, throughout document. 3. Modified Absolute Maximum Ratings (p. 5). VDD (max) 2.5V to 3.2V 4. Modified DC Recommended Operating Conditions section (p. 6). VDD (min) 1.7V to 2.37V VDD (max) 1.9V to 2.63V VDDQ (max) VDD to 1.6V
32Mb LW R-R, rev 0.6
21 / 22
March 16, 2004
SONY(R)
Rev. # rev 0.4 Rev. Date 02/05/03
CXK77K36R320GB
Description of Modification
Preliminary
5. Modified DC Electrical Characteristics section (p. 7). IMLI, ILO (min/max) 10uA to 5uA Added preliminary IDD and ISB specifications. 6. Modified AC Electrical Characteristics section (p. 8). All Bins tKHQX, tKHQX1, tKHQZ (min) 0.5ns to 0.7ns -3 tKHAX, tKHWX, tKHSX, tKHDX 0.3ns to 0.5ns -33 tKHAX, tKHWX, tKHSX, tKHDX 0.3ns to 0.6ns tKHQV 1.7ns to 1.6ns tKHQZ, tGLQV, tGHQZ, 1.9ns to 1.8ns -4 tKHAX, tKHWX, tKHSX, tKHDX 0.3ns to 0.7ns 7. Removed 1.8V VDDQ AC Test Conditions. 8. Modified JTAG DC Recommended Operating Conditions section (p. 13). VTIH (min) 1.2V to 1.4V VTIH (max) VDD + 0.3V to 3.6V VTIL (max) 0.6V to 0.8V 9. Removed 1.8V JTAG AC Test Conditions. 10. Added 2.5V JTAG AC Test Conditions (p.13). 1. Modified AC Electrical Characteristics section (p. 8). -3 tGLQV, tGHQZ -33 tGLQV, tGHQZ -4 tGLQV, tGHQZ 2. Modified JTAG ID Register definition (p. 17). Changed Part Number code from T.B.D. to 0000 0000 0111 0011. 1.7ns to 2.5ns 1.8ns to 2.5ns 2.2ns to 2.5ns
rev 0.5
07/08/03
rev 0.6
03/16/04
1. Modified I/O Capacitance section (p. 5). CIN 3.5pF to 4.0pF CKIN 3.5pF to 4.5pF COUT 4.5pF to 5.0pF 2. Modified AC Electrical Characteristics section (p. 8). All Bins tKHQX, tKHQX1, tKHQZ (min) 0.7ns to 0.65ns -3 tKHQV 1.5ns to 1.6ns tKHQZ 1.7ns to 1.8ns 3. Added note to Package Dimensions section regarding lead content in solder balls (p. 20).
32Mb LW R-R, rev 0.6
22 / 22
March 16, 2004

▲Up To Search▲

Price & Availability of CXK77K36R320GB

	To Download CXK77K36R320GB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .